The present invention relates to integrated circuits (IC), and more specifically, to integrated circuits having local maximum operating voltages to prevent gate-to-contact time-dependent dielectric breakdown (TDDB) failure.
As integrated circuits continue to be made smaller, the gate-to-contact spacing continues to decrease. While the gate-to-contact spacing has been decreasing, the operating voltage has remained fairly constant. Many currently available ICs have multiple voltage zones and employ dynamic voltage scaling to adapt to variations in workload (e.g., higher supply voltage for peak load).
TDDB failure between gates and contacts in MOSFETs has become an important reliability concern in ICs. Gate-to-contact TDDB failure occurs when the dielectric or insulator between the gate and the contact breaks down due to extended application of electric field which causes the formation of a conducting path between the gate and the contact. The likelihood of a gate-to-contact TDDB failure in a MOSFET is a function of the dimensions of the gate, the dimensions of the contact, the gate-to-contact overlay, the dielectric material between gate and contact, and the MOSFET usage including voltage, temperature and time. Due to variances in the fabrication process, the dimensions of the gate, contact and gate-to-contact overlay can vary from wafer-to-wafer, across a wafer and across the chips of a wafer. This variability of the gate-to-contact spacing across the IC affects the reliability of the IC by creating regions in the chip which will experience TDDB failure at different operating voltages.